A final product of a semiconductor substrate loaded with a large-scale semiconductor integrated circuit (LSI) is mass-manufactured using an ASIC (application specific integrated circuit) as a function device whose use is specified. When the product is designed and manufactured, a prototype is generated before the mass-manufacture.
On the semiconductor substrate as a prototype, a number of FPGAs (field programmable gate arrays) or PLDs (programmable logic devices) whose functions can be changed by a program are placed. A line connection is made among these devices, the processes are performed up to a logic debug using the prototype, and the FPGAs and the PLDs are changed into the ASIC, thus performing the procedure of a development.
In testing the above-mentioned prototype, it is necessary to conduct a sufficient test on a disconnection, a short-circuit, a defective solder joint, etc. among the devices such as a number of FPGA etc. loaded into the semiconductor substrate.
As a system for testing a prototype implemented on a substrate, a JTAG (joint test action group) system standardized as the IEEE Standard 1149.1 is used. To conduct a test in this system, it is necessary to prepare dedicated hardware, software, etc., thus requiring a large cost and a prolonged period for preparing a test circuit.
The patent document 1 describing the prior art for checking a connection line between the devices such as a number of FPGAs loaded into the substrate discloses the method of using a test circuit configured by a control circuit for generating an input pattern signal, and a shift register coupled to receive an input pattern signal from the control circuit. In this method, there is a problem that it is necessary to design a dedicated test circuit for each substrate in advance with the device configuration, the number of connection lines among the devices, external resources, etc. taken into account.
Similarly, the patent document 2 as prior art technology discloses a checking method in which comparison data corresponding to check data is generated to individually determine a line connection error etc. In this method, it is necessary to hold a large number of determination patterns for determining a result, and to provide a compression conversion circuit for determination data, memory for storing determination data, and external resources such as a connector for each FPGA for outputting a determination result. Accordingly, it is necessary to design the entire system by considering the necessary memory capacity or the necessity to add external resources.
In the conventional system for testing the connection line between the devices, it is necessary to change the test circuit depending on the connection mode among the FPGA or the number of connection lines, and check and customize the testing system for each substrate, thereby requiring specific operations and a long processing time. In addition, when external parts and external connections are required exclusively for a test, it is necessary to check the testing system before designing a substrate.    Patent Document 1: Japanese Laid-open Patent Publication No. 2000-121696 “Test Circuit for Multiple FPGA System”    Patent Document 2: Japanese Laid-open Patent Publication No. 2004-151061 “Inter-Device Connection Line Checking Method”